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Partname: | CY7B9910-5SXI |
Description: | Low Skew Clock Buffer |
Manufacturer: | Cypress Semiconductor |
Datasheet: | PDF (371K). Click here to download *) |
The completely integrated PLL enables "zero delay" capability. External divide capability, combined with the internal PLL, allows distribution of a low frequency clock that is multiplied by virtually any factor at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility. |
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Click here to download CY7B9910-5SXI Datasheet*) |
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