The CY23FP12 is a high-performance fully field-programmable 200 MHz zero delay buffer designed for high speed clock distribution. The integrated PLL is designed for low jitter and optimized for noise rejection. These parameters are critical for reference clock distribution in systems using high-performance ASICs and microprocessors. The CY23FP12 is fully programmable via volume or prototype programmers enabling the user to define an application-specific Zero Delay Buffer with customized input and output dividers, feedback topology (internal/external), output inversions, and output drive strengths. For additional flexibility, the user can mix and match multiple functions, listed in Table 2, and assign a particular function set to any one of the four possible S1-S2 control bit combinations. This feature allows for the implementation of four distinct personalities, selectable with S1-S2 bits, on a single programmed silicon. The CY23FP12 also features a proprietary auto-power-down circuit that shuts down the device in case of a REF failure, resulting in less than 50 A of current draw. The CY23FP12 provides twelve outputs grouped in two banks with separate power supply pins which can be connected independently to either a 2.5V or a 3.3V rail.