The CY27H010 is equipped with a power-down chip enable (CE) input and output enable (OE). When CE is deasserted, the device powers down to a low-power stand-by mode. The OE pin three-states the outputs without putting the device into stand-by mode. While CE offers lower power, OE provides a more rapid transition to and from three-stated outputs. The memory cells utilize proven EPROM floating-gate technology and byte-wide intelligent programming algorithms. The EPROM cell requires only 12.75 V for the supervoltage and low programming current allows for gang programming. The device allows for each memory location to be tested 100%, because each location is written to, erased, and repeatedly exercised prior to encapsulation. Each device is also tested for AC performance to guarantee that the product will meet DC and AC specification limits after customer programming. The CY27H010 is read by asserting both the CE and the OE inputs. The contents of the memory location selected by the address on inputs A16A0 will appear at the outputs O7O0.