The CY2305 and CY2309 have high drive outputs designed to meet the JEDEC SDRAM specifications of 30 pF capacitance on each DIMM clock input. Since the typical CMOS input is 7 pF and the CY2305/09 are designed to drive up to 30 pF; this means that up to 4 CMOS inputs can be driven from a single output of a CY2305/09. However the output loading on the CY2305/09 must be equal on all outputs to maintain zero delay from the input. Power Down