The baseband processing tasks are divided between the two processor cores. The DSP core executes the physical layer processing functions and the microcontroller core executes the Layer 2 and Layer 3 protocol software and the Man-Machine Interface (MMI) functions. The two cores communicate through a dedicated block of dual port memory. Each of the functional blocks in the device can be individually powered down to ensure minimum current consumption in the idle or standby mode. A block diagram of the device is provided in Figure 1. The BP is packaged in a 160-pin micro Ball Grid Array (BGA) with a 16-bit data bus and a 22-bit address bus. The package and pin configuration of the BP are shown in Figure 2. The signal pin assignments and functional pin descriptions are provided in Table 1.