The following items represent permanent changes to the specification of the CS8130 IR transceiver. 1) The Silicon Revision Register (Register 28) reads 0010, indicating rev G silicon. 2) The default receive sensitivity setting is changed to 00011 (Register 6 resets to 0011). 3) Oscillator low power mode is now the default condition after reset (Register 21 resets to 0100). 4) The BLKR bit (Register 4, bit D2) blocks the RXD output data during those periods when the transmit LEDs are on. This prevents the UART/system reading the transmitted data. The re-enable signal for the receiver is delayed by 8 s from when the LEDs are turned off. Set to 1 to block RXD data, set to 0 to allow RXD data through during transmission. This bit goes to 0 upon RESET. 5) An additional control bit was added which causes the CS8130 receiver to ignore the falling edge of the IR pulse. This bit is called ENPOS, and it is bit D2 of Register #7. ENPOS is normally 1, which causes the falling edge to be ignored. This results in greater range in IrDA and high-frequency ASK (Sharp 500 kHz) modes. ENPOS should be set to 0 for low-frequency amplitude modulated modes. 6) For IrDA/HP-SIR pulse width modes, two additional control bits have been added: a. The THIN bit (Register 7, bit D1) allows the minimum acceptable pulse width to be reduced from 1 s to 0.5 s when set to 1. This bit has effect only when the receiver is programmed to mode 1a (fixed 1.6 s pulses only) or 1c (receive 1.6 s to 3/16 of a bit cell pulses). This bit resets to 0. b. The WIDE bit (Register 1, Bit D2) expands the maximum allowable pulse width to 9/16 of a bit cell when set to 1. This bit has effect only when the receiver is set to mode 1a (fixed 1.6 s pulses only).