The architecture includes a correlated double sampler, black level clamp and a 13-bit A/D conversion module using patented DRX technology. Chip parameters can be programmed using a high speed 4-wire asynchronous digital interface. The chip outputs digitized CCD data in either 13-bit, 12bit or 10-bit format. 10-bit outputs are generated from the 13-bit A/D output by a programmable companding curve.