The PACVGA201 incorporates 7 channels of ESD protection for all signal lines commonly found in a VGA port. ESD protection is implemented with current steering diodes designed to safely handle the high surge currents encountered with IEC-61000-42 Level-4 ESD Protection (8KV contact discharge). When a channel is subjected to an electrostatic discharge, the ESD current pulse is diverted via the protection diodes into the positive supply rail or ground where it may be safely dissipated. Separate positive supply rails are provided for the VIDEO, DDC_OUT and SYNC channels to facilitate interfacing with low voltage video controller ICs and provide design flexibility in multiple-supply-voltage environments. An internal diode (D1, in schematic below) is provided such that VCC2 is derived from VCC3. (VCC2 does not require an external power supply input.) In applications where VCC3 may be powered down, diode D1 blocks any DC current path from the DDC_OUT pins back to the powered down VCC3 rail via the upper ESD protection diodes. Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the Video Controller IC (SYNC1, SYNC2). These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and VCC3. When the PWR_UP input is driven LOW the SYNC inputs can be floated without causing the SYNC buffers to draw any current from the VCC3 supply. When the PWR_UP input is LOW the SYNC outputs are driven LOW.