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| Partname: | CSPPT08-101F |
| Description: | Chip scale parallel termination array |
| Manufacturer: | California Micro Devices |
| Package: | Chip scale |
| Pins: | 8 |
| Oper. temp.: | -40 to 85 |
| Datasheet: | PDF (59K).
Click here to download *) |
The Chip Scale Package provides an ultra small footprint for this IPD and provides minimal parasitics compared to conventional packaging. Typical bump inductance is less than 25pH. The large solder bumps and ceramic substrate allow for standard attachment to laminate printed circuit boards without the use of underfill. |
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Click here to download CSPPT08-101F Datasheet*) |
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