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Partname: | AZ10LVE111EFNR2 |
Description: | 3.0 V-5.5 V, ECL/PECL 1:9 differential clock driver with enable |
Manufacturer: | |
Package: | PLCC |
Pins: | 28 |
Oper. temp.: | -40 to 85 |
Datasheet: | PDF (183K). Click here to download *) |
The AZ10/100LVE111E is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN signal is fanned-out to nine identical differential outputs. An Enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q outputs HIGH. |
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![Click here to download AZ10LVE111EFNR2 Datasheet](../../../pndecoder/datasheets/AZMIC/img/000030.gif) Click here to download AZ10LVE111EFNR2 Datasheet*) |
![](http://www.chipdocs.com/common/img/1x10t.gif) |
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