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Partname: | AZ100LVEL33DR2 |
Description: | 3.0 V-5.5 V, ECL/PECL 4 driver |
Manufacturer: | |
Package: | SOIC |
Pins: | 8 |
Oper. temp.: | -40 to 85 |
Datasheet: | PDF (193K). Click here to download *) |
The AZ10/100LVEL33 is an integrated 4 divider. The reset pin is asynchronous and clears the output (Q Low, Q High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state; the reset |
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![Click here to download AZ100LVEL33DR2 Datasheet](../../../pndecoder/datasheets/AZMIC/img/000038.gif) Click here to download AZ100LVEL33DR2 Datasheet*) |
![](http://www.chipdocs.com/common/img/1x10t.gif) |
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