The AZ100ELT23 is a dual differential PECL to CMOS/TTL translator. Because PECL (Positive ECL) levels are used, only VCC and ground are required. The small outline 8-lead packaging and the low skew, dual gate design of the ELT23 makes it ideal for applications that require the translation of a clock and a data signal. The ELT23 is available in only the ECL 100K standard. Since there are no PECL outputs or an external VBB reference, the ELT23 does not require both ECL standard versions. The PECL inputs are differential; there is no specified difference between the differential input 10K and 100K standards. Therefore the AZ100ELT23 can accept any standard differential PECL input referenced from a VCC of 3.0V to 5.5V. NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established. LOGIC DIAGRAM AND PINOUT ASSIGNMENT