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| Partname: | AZ100ELT20LR2 |
| Description: | 3.0 V-5.5 V, CMOS/TTL to differential PECL translator |
| Manufacturer: | |
| Package: | MLP |
| Pins: | 16 |
| Oper. temp.: | -40 to 85 |
| Datasheet: | PDF (201K).
Click here to download *) |
The AZ10/100ELT20 is a CMOS/TTL to differential PECL translator. Because PECL (Positive ECL) levels are used, only VCC and ground are required. The small outline packaging and the single gate of the ELT20 makes it ideal for those applications where space, performance and low power are at a premium. The ELT20 is available in both PECL standards: the 10ELT is compatible with PECL 10K logic levels while the 100ELT is compatible with PECL 100K logic levels. NOTE: Specifications in PECL tables are valid when thermal equilibrium is established. |
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Click here to download AZ100ELT20LR2 Datasheet*) |
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