The Austin Semiconductor SRAM family employs high-speed, low power CMOS designs fabricated using doublelayer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, ASI offers chip enable (CE) and output enable (OE) capability. These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE) and CE inputs are both LOW. Reading is accomplished when WE remains HIGH while CE and OE go LOW. The devices offer a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements. All devices operation from a single +5V power supply and all inputs and outputs are fully TTL compatible.