The TS68C000 reduced power consumption device dissipates an order of magnitude less power than the HMOS TS68000. The TS68C000 is an implementation of the TS68000 16/32 microprocessor architecture. The TS68C000 has a 16-bit data bus and 24-bit address bus while the full architecture provides for 32-bit address and databuses. It is completely code-compatible with the HMOS TS68000, TS68008 8-bit data bus implementation of the TS68000 and the TS68020 32-bit implementation of the architecture. Any user-mode programs written using the TS68C000 instruction set will run unchanged on the TS68000, TS68008 and TS68020. This is possible because the user programming model is identical for all processors and the instruction sets are proper sub-sets of the complete architecture.