The AT78C5009 SATA Controller bridges the conventional Parallel ATA devices with Serial ATA PHY transceivers. It includes a Serial ATA Link layer, a Transport layer, a Command Layer, two 256 x 32 FIFOs and an IDE Host/Target Controller, a Serial ATA Core and an IDE Controller, and is fully compliant with Serial ATA Gen1. The PHY block is connected to the ATA block by a 20-bit transmit and a 20-bit receive data bus. This host bridge is intended to adapt a Serial ATA Device interface to an Ultra ATA100 Host interface. Ultra DMA is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED, and PACKET commands.