The CMOS logic section provides the sequencing logic, direction, control, synchronous/asynchronous PWM operation, and a "sleep" function. The minimum CLOCK input is an ideal fit for applications where a complex P is unavailable or overburdened. TTL or LSTTL may require the use of appropriate pull-up resistors to ensure a proper input-logic high. For PWM current control, the maximum output current is determined by the user's selection of a reference voltage and sensing resistor. The NMOS outputs are capable of sinking up to 1, 2, or 3 A (depending on device) and withstanding 46 V in the off state. Clamp diodes provide protection against inductive transients. Special power-up sequencing is not required. Half-, quarter-, eighth-, and sixteenth-step operation are externally selectable for the SLA7060/61/62M. Half-step excitation alternates between the one-phase and two-phase modes (AB-B-AB-A-AB-B-ABA), providing an eight-step sequence. The Series SLA7060M is supplied in a 21-pin single in-line powertab package with leads formed for vertical mounting (suffix LF2102). The tab is at ground potential and needs no insulation. For high-current or high-frequency applications, external heat sinking may be required. This device is rated for continuous operation between -20C and +85C.