The fixed off-time pulse duration is set by user-selected external RC timing networks. The capacitor in the RC timing network also determines a user-selectable blanking window that prevents false triggering of the PWM current control circuitry during switching transitions. This eliminates the need for two external RC filter networks on the current-sensing comparator inputs. For each bridge the PHASE input controls load current polarity by selecting the appropriate source and sink driver pair. For each bridge the ENABLE input, when held high, disables the output drivers. Special power-up sequencing is not required. Internal circuit protection includes thermal shutdown with hysteresis, transient-suppression diodes, and crossover-current protection. The A3962SLB is supplied in a 20-lead plastic SOIC with copper heat sink tabs. The power tab is at ground potential and needs no electrical isolation.