The FS61857 is a low skew, low jitter CMOS zero-delay phase-lock loop (PLL) clock buffer IC. Ten differential buffered clock outputs are derived from an onboard openloop PLL. The PLL aligns the frequency and phase of all output clock pairs to the differential reference input clock CLKP/CLKN, including a feedback output clock pair that feeds back to FBINP/FBINN to close the loop. The PLL can be bypassed for test purposes by pulling AVDD to ground.