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Partname: | ASM5I9653A-32-LR |
Description: | 3.3V 1:8 LVCMOS PLL Clock Generator |
Manufacturer: | Alliance Semiconductor Corp. |
Datasheet: | PDF (648K). Click here to download *) |
The ASM5I9653A utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the ASM5I9653A requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 25 to 62.5MHz or 50 to 125MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8) and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO |
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