The devices provide a 16:1 multiplexer and clock multiplier unit. Both a high-speed serial clock and data output are generated. The devices accept 16 differential PECL data inputs and a low-speed reference clock. A unique feature of the multiplexer is that no clock is required to feed in the 16 data lines, as long as the upstream data chip clock is synchronous with the device REFCLKP/N input. Alternatively, contra-clocking may be used, whereby the device provides one of four phases of a 155.52 MHz or 166.62 MHz clock output back upstream to the data chip.