The devices contain a limiting amplifier with 30 dB gain, a clock and data recovery PLL with high-speed serial clock and data outputs, and a 1:16 demultiplexer with differential PECL data and clock outputs. The device provides improved optical receiver performance when used in optically amplified systems due to a direct slice adjust input pin and a 6 ps adjustment capability in the slicing decision time. Both devices are available in either BiCMOS or in SiGe BiCMOS technology for lower power operation.