The T7121 HDLC Interface for ISDN (HIFI-64) connects serial communications links carrying HDLC bitsynchronous data frames to 8-bit microcomputer systems. There is an optional transparent mode of operation in which no HDLC processing is performed on user data. The device communicates with the system microprocessor as a memory-mapped peripheral and is controlled by reading and writing 19 internal registers. The chip can be instructed to interrupt the microprocessor when it detects certain events requiring microprocessor attention. The HDLC transmitter and receiver are each buffered with 64-byte, first-infirst-out (FIFO) memory storage. The 64-byte buffer depth reduces the number of status polls or interrupts to be processed by the microprocessor, improving overall system efficiency. The major blocks are the microprocessor interface, transmit and receive FIFO memory buffers, HDLC processor, and a concentration highway interface (see Figure 1). The T7121 device is available in a 28-pin, plastic DIP or a 28-pin, plastic, small-outline, J-lead (SOJ) package for surface mounting.