|
|
|
|
| Partname: | OR3LP26BM680I |
| Description: | ORCA feild-programmable system chip embedded master/target PCI interface. 32-/64-bit, 33/66 MHz PCI bus interface with 64-bit back-end data path in each direction. Array size 18 x 28. |
| Manufacturer: | Agere Systems |
| Package: | PBGAM |
| Pins: | 680 |
| Oper. temp.: | -40 to 85 |
| Datasheet: | PDF (5M).
Click here to download *) |
The embedded core and interface comprise approximately 85K standard-cell ASIC gates in addition to these usable gates. The usable gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. |
|
Click here to download OR3LP26BM680I Datasheet*) |
 |
| *)Datasheets downloading from ChipDocs is only for our members (paid service). REGISTER NOW for your membership. |
|
|
|
