The LCK4310, as with most ECL devices, can be operated from a positive voltage supply (VDD) in LVPECL mode. This allows the LCK4310 to be used for high-performance clock distribution in 3.3 V/2.5 V systems. Designers can take advantage of the LCK4310's performance to distribute lowskew clocks across the backplane or the board. In a PECL environment (series or Thevenin), line terminations are typically used since they require no additional power supplies. If parallel termination is desired, a terminating voltage of VDD 2.0 V will need to be provided.