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Description:PLL-Based Clock Recovery Circuit, for Data Rates In Excess Of 90 Mbps, Loop Bandwidth of 0.08% of Center Frequency
Manufacturer:Analog Devices
Datasheet:PDF (253K).
Click here to download *)

The AD800 and AD802 employ a second order phase-locked loop architecture to perform clock recovery and data retiming on Non-Return to Zero, NRZ, data. This architecture is capable of supporting data rates between 20 Mbps and 160 Mbps. The products described here have been defined to work with standard telecommunications bit rates. 45 Mbps DS-3 and 52 Mbps STS-1 are supported by the AD800-45 and AD800-52 respectively. 155 Mbps STS-3 or STM-1 are supported by the AD802-155.

Click here to download AD802 Datasheet
Click here to download AD802 Datasheet
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