The AD7835 can accept either 14-bit parallel loading or doublebyte loading, where right-justified data is loaded in one 8-bit byte and one 6-bit byte. Data is loaded from the external bus into one of the input latches under the control of the WR, CS, BYSHF, and DAC channel address pins, A0 to A2. With each device, the LDAC signal is used to update all four DAC outputs simultaneously, or individually, on reception of new data. In addition, for each device, the asynchronous CLR input can be used to set all signal outputs, VOUT1 to VOUT4, to the user-defined voltage level on the Device Sense Ground pin, DSG. On power-on, before the power supplies have stabilized, internal circuitry holds the DAC output voltage levels to within 2 V of the DSG potential. As the supplies stabilize, the DAC output levels move to the exact DSG potential (assuming CLR is exercised).