The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS, and the conversion is also initiated at this point. There are no pipeline delays associated with the part. The reference for the part is taken internally from VDD. This allows the widest dynamic input range to the ADC. Thus, the analog input range for the part is 0 V to VDD. The conversion rate is determined by the SCLK. 1