The full-scale output voltage is determined by the applied external reference input voltage, VREF. The rail-to-rail VREF input to VOUT outputs allows for a full-scale voltage set equal to the positive supply VDD or any value in between. A doubled-buffered serial data interface offers high speed, microcontroller compatible inputs using serial-data-in (SDI), clock (CLK) and load strobe (LDA + LDB) pins. A chip-select (CS) pin simplifies connection of multiple DAC packages by enabling the clock input when active low. Additionally, an RS input sets the output to zero scale or to 1/2 scale based on the logic level applied to the MSB pin. The power shutdown pin, SHDN, reduces power dissipation to nanoamp current levels. All digital inputs contain Schmitt-triggered logic levels to minimize power dissipation and prevent false triggering on the clock input.