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Partname:AD6620AS
Description:65 MSPS Digital Receive Signal Processor
Manufacturer:Analog Devices
Datasheet:PDF (354K).
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The AD6620 is a digital receiver with four cascaded signalprocessing elements: a frequency translator, two fixedcoefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compatible. As ADCs achieve higher sampling rates and dynamic range, it becomes increasingly attractive to accomplish the final IF stage of a receiver in the digital domain. Digital IF Processing is less expensive, easier to manufacture, more accurate, and more flexible than a comparable highly selective analog stage. The AD6620 diversity channel decimating receiver is designed to bridge the gap between high speed ADCs and general purpose DSPs. The high resolution NCO allows a single carrier to be selected from a high speed data stream. High dynamic range decimation filters with a wide range of decimation rates allow

Click here to download AD6620AS Datasheet
Click here to download AD6620AS Datasheet
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