The MC-ACT-G704E1 Framer core is designed to handle synchronous frame structures (Recommendation G.704) running on an E1 carrier. Transmitter and receiver part are two completely independent blocks both capable of handling basic and multi frames. Both perform functions such as overhead bit insertion / detection, CRC4 computation and check. A very flexible synchronization unit (Recommendation G.706) synchronizes automatically or by means of an external frame sync signal. The frame builder unit can be configured which of the overhead bits are to be inserted or not. Avnet Memec cores are designed with the philosophy that no global elements should be embedded within the core itself. Global elements include any of the following components: STARTUP, STARTBUF, BSCAN, READBACK, Global Buffers, Fast Output Primitives, IOB Elements, Clock Delay Components, and any of the Oscillator Macros. Avnet Memec cores contain resources present in only the sequential and combinatorial array. This is done to allow flexibility in using the cores with other logic. For instance, if a global clock buffer is embedded within the core, but some external logic also requires that same clock, then an additional global buffer would have to be used. In any instance, where one of our cores generates a clock, that signal is brought out of the core, run through a global buffer, and then brought back into the core. This philosophy allows external logic to use that clock without using another global buffer. A result of this philosophy is that the cores are not self-contained. External logic must be connected to the core in order to complete it.