| CD54HC112F3A | HIGH SPEED CMOS LOGIC DUAL J-K FLIP-FLOPS WITH SET AND RESET, NEGATIVE-EDGE TRIGGER in 16-pin J package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD54HCT112F3A | HIGH SPEED CMOS LOGIC DUAL J-K FLIP-FLOPS WITH SET AND RESET, NEGATIVE-EDGE TRIGGER in 16-pin J package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HC112E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET in 16-pin N package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HC112M96 | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET in 16-pin D package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HCT112E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET in 16-pin N package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD54HC112 | Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | Datasheet*) |
| CD54HCT112 | Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | Datasheet*) |
| CD74HC112MT | Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | Datasheet*) |
| CD74HC112NSR | Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | Datasheet*) |
| CD74HC112PW | Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | Datasheet*) |
| CD74HC112PWR | Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | Datasheet*) |
| CD74HC112PWT | Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | Datasheet*) |
| CD74HC112 | Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | Datasheet*) |
| CD74HCT112 | Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | Datasheet*) |
| 5962-8970201EA | High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge Trigger | Datasheet*) |
| CD74HC112EE4 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset | Datasheet*) |
| CD74HC112M96E4 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset | Datasheet*) |
| CD74HC112MTE4 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset | Datasheet*) |
| CD74HC112NSRE4 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset | Datasheet*) |
| CD74HC112PWE4 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset | Datasheet*) |
| CD74HC112PWRE4 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset | Datasheet*) |
| CD74HC112PWTE4 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset | Datasheet*) |
| CD74HCT112EE4 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset | Datasheet*) |
