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CD74HC10 series datasheets. Manufacturer: Texas Instruments.

CD54HC107F3A HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE TRIGGER J-K FLIP-FLOPS WITH RESET in 14-pin J package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD74HC107E HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET in 14-pin N package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD74HC107M HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET in 14-pin D package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD74HC107M96 HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET in 14-pin D package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD74HCT107E HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET in 14-pin N package. Operational temperature range from -55°C to 125°C.Datasheet*)
5962-9070101MEA HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE TRIGGER J-K FLIP-FLOPS WITH SET AND RESET in 16-pin J package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD54HC109F3A HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE TRIGGER J-K FLIP-FLOPS WITH SET AND RESET in 16-pin J package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD54HCT109F3A HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE TRIGGER J-K FLIP-FLOPS WITH SET AND RESET in 16-pin J package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD74HC109E HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET in 16-pin N package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD74HC109M HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET in 16-pin D package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD74HC109M96 HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET in 16-pin D package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD74HCT109E HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET in 16-pin N package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD74HCT109M HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET in 16-pin D package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD74HCT109M96 HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET in 16-pin D package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD54HC10F HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin J package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD54HC10F3A HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin J package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD54HCT10F3A HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin J package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD74HC10E HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin N package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD74HC10M HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin D package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD74HC10M96 HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin D package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD74HCT10E HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin N package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD74HCT10M HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin D package. Operational temperature range from -55°C to 125°C.Datasheet*)
CD74HCT10M96 HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin D package. Operational temperature range from -55°C to 125°C.Datasheet*)
5962-8984301CAHigh-Speed CMOS Logic Triple 3-Input NAND GateDatasheet*)
CD54HC10High-Speed CMOS Logic Triple 3-Input NAND GateDatasheet*)
CD54HCT10High-Speed CMOS Logic Triple 3-Input NAND GateDatasheet*)
CD74HC10MTHigh-Speed CMOS Logic Triple 3-Input NAND GateDatasheet*)
CD74HCT10MTHigh-Speed CMOS Logic Triple 3-Input NAND GateDatasheet*)
CD54HC107Dual J-K Flip-Flop with Reset Negative-Edge TriggerDatasheet*)
CD74HC107MTDual J-K Flip-Flop with Reset Negative-Edge TriggerDatasheet*)
CD54HC109Dual J-K Flip-Flop with Set and Reset Positive-Edge TriggerDatasheet*)
CD54HCT109Dual J-K Flip-Flop with Set and Reset Positive-Edge TriggerDatasheet*)
CD74HC109MTDual J-K Flip-Flop with Set and Reset Positive-Edge TriggerDatasheet*)
CD74HCT109MTDual J-K Flip-Flop with Set and Reset Positive-Edge TriggerDatasheet*)
CD74HC10High Speed CMOS Logic Triple 3-Input NAND GateDatasheet*)
CD74HCT10High Speed CMOS Logic Triple 3-Input NAND GateDatasheet*)
CD74HC107Dual J-K Flip-Flop with Reset Negative-Edge TriggerDatasheet*)
CD74HCT107Dual J-K Flip-Flop with Reset Negative-Edge TriggerDatasheet*)
CD74HC109Dual J-K Flip-Flop with Set and Reset Positive-Edge TriggerDatasheet*)
CD74HCT109Dual J-K Flip-Flop with Set and Reset Positive-Edge TriggerDatasheet*)
5962-8515401CAHigh Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with ResetDatasheet*)
9084901MCADual J-K Flip-Flop with ResetDatasheet*)
CD54HCT107Dual J-K Flip-Flop with ResetDatasheet*)
CD74HC107EE4High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with ResetDatasheet*)
CD74HC107M96E4High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with ResetDatasheet*)
CD74HC107ME4High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with ResetDatasheet*)
CD74HC107MTE4High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with ResetDatasheet*)
CD74HCT107EE4High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with ResetDatasheet*)
CD74HC10EE4High Speed CMOS Logic Triple 3-Input NAND GatesDatasheet*)
CD74HC10M96E4High Speed CMOS Logic Triple 3-Input NAND GatesDatasheet*)
CD74HC10ME4High Speed CMOS Logic Triple 3-Input NAND GatesDatasheet*)
CD74HC10MTE4High Speed CMOS Logic Triple 3-Input NAND GatesDatasheet*)
CD74HCT10EE4High Speed CMOS Logic Triple 3-Input NAND GatesDatasheet*)
CD74HCT10M96E4High Speed CMOS Logic Triple 3-Input NAND GatesDatasheet*)
CD74HCT10ME4High Speed CMOS Logic Triple 3-Input NAND GatesDatasheet*)
CD74HCT10MTE4High Speed CMOS Logic Triple 3-Input NAND GatesDatasheet*)
CD74HC109EE4High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and ResetDatasheet*)
CD74HC109M96E4High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and ResetDatasheet*)
CD74HC109ME4High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and ResetDatasheet*)
CD74HC109MTE4High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and ResetDatasheet*)
CD74HCT109EE4High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and ResetDatasheet*)
CD74HCT109M96E4High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and ResetDatasheet*)
CD74HCT109ME4High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and ResetDatasheet*)
CD74HCT109MTE4High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and ResetDatasheet*)
Click here to download CD74HC10 Datasheet
Click here to download Datasheet
*)

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