CD54HC73F | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE TRIGGER J-K FLIP-FLOPS WITH RESET in 14-pin J package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
CD54HC73F3A | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE TRIGGER J-K FLIP-FLOPS WITH RESET in 14-pin J package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
CD74HC73E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET in 14-pin N package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
CD74HC73M | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET in 14-pin D package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
CD74HC73M96 | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET in 14-pin D package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
CD74HCT73E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET in 14-pin N package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
CD74HCT73M | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET in 14-pin D package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
5962-8515301CA | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Datasheet*) |
CD54HC73 | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Datasheet*) |
CD74HC73EE4 | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Datasheet*) |
CD74HC73M96E4 | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Datasheet*) |
CD74HC73ME4 | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Datasheet*) |
CD74HC73MT | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Datasheet*) |
CD74HC73MTE4 | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Datasheet*) |
CD74HCT73EE4 | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Datasheet*) |
CD74HCT73ME4 | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Datasheet*) |