| 74LV107D | Dual JK flip-flop with reset; negative-edge trigger | Datasheet*) |
| 74LV107DB | Dual JK flip-flop with reset; negative-edge trigger | Datasheet*) |
| 74LV107N | Dual JK flip-flop with reset; negative-edge trigger | Datasheet*) |
| 74LV107PW | Dual JK flip-flop with reset; negative-edge trigger | Datasheet*) |
| 74LV109D | Dual JK(not) flip-flop with set and reset; positive-edge trigger | Datasheet*) |
| 74LV109DB | Dual JK(not) flip-flop with set and reset; positive-edge trigger | Datasheet*) |
| 74LV109N | Dual JK(not) flip-flop with set and reset; positive-edge trigger | Datasheet*) |
| 74LV109PW | Dual JK(not) flip-flop with set and reset; positive-edge trigger | Datasheet*) |
| 74LV10D | 3.6 V, Triple 3-input NAND gate in 14-pin SO package. Operational temperature range from -40°C to 125°C. | Datasheet*) |
| 74LV10DB | 3.6 V, Triple 3-input NAND gate in 14-pin SSOP package. Operational temperature range from -40°C to 125°C. | Datasheet*) |
| 74LV10N | 3.6 V, Triple 3-input NAND gate in 14-pin DIL package. Operational temperature range from -40°C to 125°C. | Datasheet*) |
| 74LV10PW | 3.6 V, Triple 3-input NAND gate in 14-pin TSSOP package. Operational temperature range from -40°C to 125°C. | Datasheet*) |
| 74LV10 | Triple 3-input NAND gate | Datasheet*) |
| 74LV10PWDH | Triple 3-input NAND gate | Datasheet*) |
| 74LV107 | Dual JK flip-flop with reset; negative-edge trigger | Datasheet*) |
| 74LV107PWDH | Dual JK flip-flop with reset; negative-edge trigger | Datasheet*) |
| 74LV109 | Dual JK flip-flop with set and reset; positive-edge trigger | Datasheet*) |
| 74LV109PWDH | Dual JK flip-flop with set and reset; positive-edge trigger | Datasheet*) |
