CD54HC107F3A | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE TRIGGER J-K FLIP-FLOPS WITH RESET in 14-pin J package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
CD74HC107E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET in 14-pin N package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
CD74HC107M | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET in 14-pin D package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
CD74HC107M96 | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET in 14-pin D package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
CD74HCT107E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET in 14-pin N package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
CD54HC107 | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Datasheet*) |
CD74HC107MT | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Datasheet*) |
CD74HC107 | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Datasheet*) |
CD74HCT107 | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Datasheet*) |
5962-8515401CA | High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset | Datasheet*) |
9084901MCA | Dual J-K Flip-Flop with Reset | Datasheet*) |
CD54HCT107 | Dual J-K Flip-Flop with Reset | Datasheet*) |
CD74HC107EE4 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset | Datasheet*) |
CD74HC107M96E4 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset | Datasheet*) |
CD74HC107ME4 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset | Datasheet*) |
CD74HC107MTE4 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset | Datasheet*) |
CD74HCT107EE4 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset | Datasheet*) |